1. Field of the Invention
The present invention is generally in the field of switch mode power supply control systems. More specifically, the present invention is in the field of combining open loop and closed loop pulse width modulation or pulse frequency modulation control operating within a digital control system for a power supply.
2. Background Art
Many years of research in switch mode power supply controller design have lead to a multitude of schemes that exist within the topology of closed loop control systems. The inventor of the present invention has recently invented power supply control systems that comprise both open loop and optionally, closed loop topology. For instance, the invention of U.S. Pat. No. 6,940,189 teaches open loop control based on pulse width modulation or pulse frequency modulation derived from comparing a frequency dividing clock counter value to a table of values corresponding to the present power state of the system under control based on predetermined characterization data of the system. Having predetermined characterization data affords the designer the opportunity to implement an open loop topology of precise control that also saves component cost and reduce circuit cost and complexity. Additionally, the specification of U.S. Pat. No. 6,940,189 also describes binary input pads into the controller availing means of offsetting the entries in the table and thus providing closed loop control based on empirical data. Furthermore, the inventions described in World Intellectual Property Organization Publications numbered WO 2008/048865 A2 and WO 2008/060850 A2 teach structures and methods of implementing pulse width modulation control systems generating pulse sequences that provide a near critical damped step response and maintain a maximally flat voltage during current transients in such systems respectively. The specification in the World Intellectual Property Organization Publication numbered WO 2008/048865 A2 explicitly illustrates such a system fixed in both open loop and closed loop topologies.
There exists a multitude of switch mode power supply control systems comprising closed loop topology, each offering unique advantages such as proprietary or public domain design concepts reducing cost of design implementation, design reuse, and design sustaining, thus reducing cost of market entry and time-to-market to each purveyor of such proprietary or public domain designs. Most of these designs likely satisfactorily meet the requirements of precise steady state voltage regulation in environments subject to stochastic variation such as temperature drift necessitating closed loop topology control systems. However, these proprietary or public domain closed loop control system designs could achieve higher energy efficiency or lower component cost if, during most of the steady state operation, the components comprising the feedback and/or feed forward loops could be powered-down, or shared amongst other controllers powering other voltage domains. Furthermore, these proprietary or public domain closed loop control system designs would benefit from the assurance of attaining a critical damped step response during a power state transition of the system under control. Attaining a critical damped step response assures the fastest possible response time when providing power to loads typically requiring precise voltage regulation such as semiconductor cores, typically tolerating voltage excursions of five percent or less beyond their given set-point. For instance, a practical benefit of meeting the fastest possible response time thus allows such devices to go into sleep mode quicker and more often, and of course, come out of sleep mode faster, an optimal means to reduce costs and enhance power efficiency of the total system-on-chip solution.
Therefore, there exists a need for a structure which combines the benefits of proprietary or public domain closed loop topology power supply control systems for steady state operation while attaining the high power efficiency of an open loop structure generating a near critical damped step response during system power state transitions and/or maintaining a maximally flat voltage during current transients.